DesignCon 2006 Functional Verification of 622-Mbps–6.375-Gbps Transceiver IP in an FPGA
نویسندگان
چکیده
The process of verifying a configurable IP is more complex and time-consuming than the IP design. This paper discusses a “divide-and-conquer” functional verification methodology for a highly configurable multi-gigabit transceiver IP used in a FPGA. Verification methods, reusability, hardware emulation and mixed-signal validation are covered to show how the IP is efficiently verified for tape-out. The advantages of the presented method include comprehensive test coverage, test bench re-usability in chip simulations, hardware emulation and lab bring up, and improved verification efficiency.
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